1. Field of the Invention
The present invention relates to synchronization of data, and more particularly, to a low latency method of synchronizing high-speed data between two clock domains having respective clocks generated from the same timebase and having a prescribed frequency relationship.
2. Background Art
Newer communications systems require advanced processing of high speed digital signals in order to accommodate precise timing requirements. For example, processor-based communications systems utilize high speed bus architectures, such as HyperTransport™ bus architectures, to transfer large groups of data at high data rates. For example, the HyperTransport™ Specification specifies data transfer between discrete components (e.g., between a microprocessor and a PCI bridge) in data groups (packets) of up to 64 bytes, at prescribed data rates of 400 Megabits per second (Mbs) up to 2.0 Gigabits per second (Gbs) per wire.
In some high speed bus architectures, such as HyperTransport™, it is required that the frequency of the transmit bus (i.e., the transmit clock domain) be programmable and changeable within a running system. However, it is also often the case that it is not desired to change the clock frequency at which the remainder of the local chip runs (i.e., the local clock domain), perhaps because it connects to another bus of a specific defined frequency, or has been tuned to run most efficiently at a particular frequency. The local clock domain may also run at a much slower frequency than the transmit clock domain. Accordingly, there is a need to synchronize data from the local clock domain to the transmit clock domain.
In many applications both the local and transmit clocks are generated from a single timebase, given by a single clock input, and passed through 2 different phase locked loop (PLL) circuits to generate the two different target frequencies. Averaged over a long period of time, these target frequencies will be in a simple ratio, given by the ratio of the dividers in the PLL circuits. However, the PLL circuits will induce jitter (both correlated and uncorrelated between the PLLs) across the target clocks, causing the clocks to move relative to their ideal alignment to the reference and each other.
Techniques for synchronizing data between the local and transmit clock domains generated from a common timebase have included gearboxes and sync FIFOs with synchronized valid bits. Gearboxes only work, however, if the clock frequencies are small multiples of each other, such that the minimum time for data to from any local clock edge to any transmit clock edge provides enough time for the data to propagate from a flip-flop clocked by the local clock to a flip-flop clocked by the transmit clock and make setup there, in the presence of jitter. Hence, gearboxes cannot be used for arbitrary frequency ratios between the local clock and transmit clock. Synchronizing valid bits works across any ratio of frequencies, but introduces the latency required to do the synchronization.